Power Device Design Verification
Utilizing the edge-based 3D solver, optimizing Rdson and gate delay in power transistor arrays
Verifying current density "hot-spots", checking electro-migration violation
Optimizing layout and pad placement, detecting missing vias and metal current crowding
Extending to power device die, package, and PCB co-simulation, ensuring an optimal thermal performance
Integrated with user-friendly results viewer with cross-linked reports and field views
High precision parameter extraction
and optimization
2D view, solver view,
and field view
Analyze pad
and via placement
Analyze potential issues like electromigration,
overheating failures, etc.
Simulation based transient
ET analysis
Maximize switching
frequency
Power device
design analysis(IGBT)
Automotive IC
design analysis
Power IC design analysis (PMIC/
DC-DC converters)
Mixed-signal IC
design analysis
Co-optimization of ET performance(in
Chip/Package/PCB)
High voltage
GAN device
design analysis